Low Kickback Noise and High Speed Multi Stage Comparator for High Speed SAR ADC’s

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Abstract

In this paper, proposes the design of a high-speed, low-kickback, three-stage comparator built on CMOS technology. This 1.2V supply-operated comparator circuit develops for use in high-speed ADCs. There are three parts to the proposed comparator circuit: a preamplifier, a latch, and a regeneration stage. The input signal amplifies in the preamplifier stage, producing a differential output signal. Once the movement from the preamplifier (PA) stage strengthens, it is stored in the latch stage until the regeneration stage is ready to utilize—simulations in CMOS technology to test the suggested comparator circuit. The voltage gain and switching speed of the three-stage comparator in this research improve over the standard two-stage comparators. The LT spice simulation results exhibit the proposed comparator circuit's fast speed, minimal backlash, and low power consumption.

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Keywords

Analog to digital converter (ADC); CMOS Technology; Comparator; Kick back noise; Pre amplifier (PA)