Secure Hash Algorithm SHA-256 Based Hardware Acceleration Using Spartan-6

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Abstract

Recently, there have been many technological advancements in communication, particularly in online transactions, increasing the necessity for highly secure networks and transactions. The number of cryptographic algorithms has expanded. Cryptographic hash functions are used to secure and authenticate data and transactions. SHA-256 (Secure Hash Algorithm-256) is a one-way hash function that is both secure and quick, with a high collision resistance. In this work SHA-256 hardware architecture with minimal power consumption and area based on a sequential calculation of the message scheduler and working variables. The hardware was designed in HDL and built on a SPARTAN-6 FPGA, which provides exceptional efficiency and performance. Different optimization techniques, such as gated clock conversion, arithmetic resource sharing, and structural modelling of small building blocks, were employed to further reduce power and area. The proposed design ran with a maximum frequency of 83.33 MHz the implementation reports indicated a dynamic power consumption of 14 mW and area utilization of 505 slices while maintaining a good throughput of 2659.42 G bits/s and a relatively high efficiency of 5.266 M bits/s per slice.

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Keywords

Acceleration; Cryptographic; FPGA; Hash; Secure; Throughput.