ASIC Design using Post Route ECO Methodologies for Timing Closure and Power Optimization

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Abstract

This paper presents work for timing and power optimization in ASIC in the post route phase. The current challenges of maintaining performance have led to research into alternative paradigms and complex design processes. Post-route design modifications are one of them and they are complex, timeconsuming, and potentially disrupt physical synthesis, leading to routing bottlenecks and many other design issues. Fixing design constraints, verifying exhaustively, and reverting to synthesis stages can be time-consuming. This work discusses major post-route issues like electromigration, crosstalk, and antenna effects, as well as clock and Datapath optimization for timing closure. The work uses existing techniques to address these issues effectively by generating manual ECO, ensuring proper functioning of the chip, and promoting signal integrity all along the design process. This work also illustrated the effect of each step on the timing, power numbers and the cell utilization. Furthermore, the research has shown that harnessing existing traditional techniques, combined with a meticulous approach to selecting the optimal fixes through thorough verification, can significantly streamline the design signoff process.

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Keywords

Antenna effect; Cell characteristics; Crosstalk; ECO; Power optimization; Signal integrity; Timing closure; Verification