Design of an Efficient Selective Stochastic Model for Delay-Aware Digital Classification using Nexys A7 FPGA

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Abstract

As the dimension of the speech recognition dataset increases while performing the classification of the same, results in an increment of several features as well as its classification delay. Therefore, to reduce the delay required during the classification, this paper proposes the Selective Stochastic Model for delay-aware Digital Classification (SSMDC) which consists of a Gold Code-based Intelligent Pseudo Stochastic Number Generator (GCI PSNG) followed by Message Digest 5 (MD5) model. The role of the PSNG model is to generate efficient sample indices for classification into different categories followed by a low-complexity truncated MD5 model for the generation of sample-selection indices. These indices are sequentially given to feature memory blocks for the selection of samples, which are classified by the underlying classifiers. The SSMDC model performance is tested on auditory Mel-Frequency Cepstral Coefficients (MFCC) component features with k-Nearest Neighbors (k-NN) classifier but can be extended to any other application with minimal configurations, thereby making it useful for a wide variety of real-time scenarios. The proposed model is implemented using Verilog HDL on Xilinx Vivado Design Suite 2023.1, and simulation results are obtained considering the device xc7a100tcsg324-1 Nexys A7 FPGA. Also, with SSMDC, the proposed model reduces the delay of classification by 27.35% when compared with other classification models.

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Keywords

Message Digest 5 (MD5); Mel Frequency Cepstral Coefficients (MFCC); Pseudo Stochastic Number Generator (PSNG); Speech Classification.