A Lightweight Hardware Accelerator for Weather Prediction using Vitis HLS and Linear Regression

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Abstract

This paper presents a lightweight hardware accelerator for weather prediction based on linear regression, implemented using Vitis High-Level Synthesis (HLS) targeting the Arty A7 FPGA. The design utilizes historical weather data to predict temperature and humidity while evaluating R-squared (R²) and Mean Squared Error (MSE) for accuracy. The design is synthesized and co-simulated within Vitis HLS, exported as RTL, and successfully integrated into Vivado as a reusable IP. Performance is compared against Python-based models to highlight the advantages of FPGA acceleration in the VLSI domain. Resource utilization metrics such as LUTs, FFs, BRAMs, and DSPs are analyzed. Results confirm the feasibility and efficiency of Vitis HLS for real-time, low-power weather forecasting systems

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Keywords

Vitis HLS, FPGA, Weather Prediction, Parallel Processing, Simulation, Synthesis, CPP, Co-simulation, Implementation, Vivado, Linear Regression, Python, RTL Generation, Arty A7, Resource Utilization, Mean Square Error, R-Squared, IP block.